Hrushikesh Badgujar
Design Engineer II @Cadence || Physical Design Engineer || M.Tech in VLSI Design || NIT Surat’24
- Role
- Design Engineer Ii at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Hrushikesh Badgujar
Good Understanding of ASIC design flow.> Responsible for Physical design implementation for High Speed Memory IP\'s (HBM)> Experienced in Physical Design. I possess comprehensive knowledge spanning Floorplanning, Place and Route, Clock Tree Synthesis, Synthesis, Routing, Static Timing Analysis, ECO Implementation, EM-IR and Physical Verification.> Hands-on experience with Cadence Innovus, Tempus, Synopsys ICC2 compiler, PrimeTime through relevant projects.> Additionally, my knowledge extends to Verilog, Linux and Basics of TCL languages.> Strong engineering professional with a Master of Technology (M.Tech) in VLSI from NIT Surat.
Experience
Design Engineer Ii
Aug 2024 — Present · Bengaluru, IN
Handling block level physical design implementation starting from floorplaning to GDS-II alongside closure on Timing, DRC\'s and EM-IR violations.2. Tool - Innovus, Tempus, and other company proprietary internal tools.
Education
National Institute of Technology Surat
M.Tech, VLSI Design
SIES High School Matunga Mumbai
Schooling- SSC
University of Mumbai- Terna Engineering College
Bachelor of Engineering - BE, Electronic and Telecommunications Engineering
2018 — 2022
SIES College of Arts, Science & Commerce SION(W)
Intermediate studies-HSC
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