Howard Yang

About Howard Yang

Define and drive ASIC power efficiency and optimization methodology from architecture to implementation and sign-off.• Analysis and optimize RTL and gate level design including tools like Ansys Power Artist, DC and PTPX• Collaborate with cross-functional teams to drive power reduction across the platform, including Architecture, Design, Verification and Silicon Validation• Set power efficiency targets for power modes and provide power estimation for blocks and full chip • Create ASIC Power Model by extract key metrics from Power Artist and PTPX. • Power intent design w/ UPF: Incl block & toplevel implementation, integration, verification and sign-off thru VCLP, DC, VCS, Formality on RTL and netlist.• Develop methodology and tool flow to drive power efficiency improvement. Working with tool vendors (Synopsys/Cadence/Ansys) to address any power-related tool issues.• Deliver training to various chip teams on low power topics and provide support and code review sessions.• Provide post silicon bringup/validation support and debug

Experience

1. Asic Power Engineer

   Google

   May 2021 — Present · Mountain View, CA, US

Education

• The University of British Columbia

  Bachelor’s Degree, Computer Engineering

  1996 — 2001

• The University of British Columbia

  M.Eng, Electrical & Computer Engineering

  2008

Skills

• Bash
• Debugging
• Mixed Signal
• Upf Low Power Design
• Semiconductors
• Tcl
• Analog
• Rtl Design
• Unix Shell Scripting
• Static Timing Analysis
• Cadence Virtuoso
• Vlsi
• Cad
• Cmos
• Integrated Circuits (Ic)
• Ic
• Application-Specific Integrated Circuits (Asic)
• Redhat
• Perl Script
• Soc
• Asic