Hongshuo W.

About Hongshuo W.

In-depth knowledge of Semiconductor Physics, Design, Layout, Circuits, Fabrication, Characterization. •20••••25: semiconductor device development for integrated circuit product tapeout. •Tapeout Skills: Synopsys Sentaurus TCAD, Cadence Virtuoso, Cadence Skill, Calibre DRC, BIAS, LVS, PDK, Design Rule, Process Flow, LabView, Java, R, Linux. •20••••22: Automated Testing Equipment (ATE) SmarTest.•20••••19 in Prof. Hiroshi Amano’s group (2014 Nobel Prize laureate in Physics): 4 years experience in crystal growth, thin-film deposition, device layout, and semiconductor device characterization, proficient with nitrides (GaN, AlGaN, h-BN, InN), LEDs, semiconductor lasers. •20••••21 at the University of Notre Dame: 2 years experience in semiconductor TCAD simulation, Cadence layout, device fabrication, and GaN-based power devices. •9+ years’ characterization experience in electrical and optical on semiconductors: DC, AC, HCI, HHI, HTOL, ESD reliability, TLP, AFM, SEM, TEM, FIB, EDX, EBSD, XRD, XPS, FT-IR, SIMS, Hall effect, microscope, DLTS/MCTS, ellipsometer, PL, CL, spectrometers, emission microscope, Raman spectroscopy, profilometer, Filmetrics, TLM, oscilloscope. •9+ years’ cleanroom experience of crystal growth & device fabrication: MOCVD, sputtering, ALD, E-beam evaporation, PECVD, HVPE, MBE, sublimation, furnace, carbon coater, RIE etching, annealing, ion implantation, EBL, lithography, CMP, RCA. •Languages: English (fluent), Japanese (native, JLPT level N1), Chinese (native).

Experience

1. Senior Engineer

   Analog Devices

   Dec 2022 — Present · San Francisco, CA, US

   Be responsible for multiple CMOS/DMOS semiconductor devices & technologies development projects for integrated circuit products, including TCAD simulation design, Cadence layout generation, tape-out process, and electrical characterization. Executed layout flow by Cadence Skill & Virtuoso: layer, PCell, routing generation, Topcell integration, connectivity check.Performed layout verifications: Calibre DRC, LVS, BIAS; involved in PDK, Design Rule, Process Flow updating. Hand-on device characterization in engineering labs & Production Test Floor: DC, HCI, HHI, TLP, HTOL, ESD reliability. Collaborated with cross-functional teams to manage cost-effective engineering solutions for multiple projects. Awarded Blue Diamond Award for cost effective solutions in power semiconductor applications.