Hojeong Lim
Director of Ic Packaging Design @Amkor Technology, Inc.
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WORK HISTORY
Director of Ic Packaging Design @Amkor Technology, Inc.
US
Qualcomm Interface for new product package selection based on requirements for mechanical, thermal, and electrical performance to achieve the lowest system-level cost. Lead device IO / Package co-design activity for advanced Package. PI/SI optimization at entry packaging design level Utilize device design expertise to drive power/performance efficient future memory package solution. Perform package and PCB design collaboration feasibility study and provide feedback to chip designer during the developmental stage on device floor plan. Interface with PCB designer on routing trade-off analysis of PCB layer stack-up, layer counts and manufacturing technologies based on different pin map assignments and pin depopulation scheme scenarios to achieve the lowest system cost solution. Provide the guidance to product development teams and Qualcomm- SWIFT ( Silicon Wafer Integrated Fanout Technology)- Wafer Level Fan Out Design with PoP (Mobile AP) Compatible, SWIFT DFM( Design For Manufacturing) and Setup Design review and process flow- Mobile AP (Application Processor) with MEP(MCeP) and PoP (Package on Package)- fc-SIP Module- Wafer Level Package and eWLB- Coreless substrate and ETS (Embedded Trace Substrate)- EPS (Embedded Passive Substrate)- Cu-Block in Substrate
EDUCATION
Hanyang University
MS, Electronics
ABOUT HOJEONG LIM
Build and manage a cross-functional team of package designers across multiple locations and with expertise in all different domains: EM, SI/PI, Thermal, and layout. Manage day-to-day project tasks, make decisions on package design, run simulations to verify performance, and work cross-functionally with the silicon team to guide the technical execution of cutting-edge product from inception to design, test, qualification, and HVM. 20+ years of industry experience in Semiconductor Foundry & Packaging Design/Integration, from idea & concept to final product through Package design, Material selection, and Product qualification. Experience with Mobile Application Processor and Memory interface in PoP / MEP (Package stack), WLFO(Wafer Level Fan-Out), WLP(Wafer Level Package) and Network System in FCBGA Experience working with physical design parameters affecting the electrical and thermal performance of packaging technologies. DFM & PCB substrate qualification and supply chain management: In-depth knowledge of PCB process Customer Interface for Packaging Design Service and driving projects requiring a timely response to customer’s demand. The Knowledge of transmission line and electromagnetic theory related to signal integrity(SI) and power integrity(PI) Specialties: Cu Pillar, PoP, Wafer Level Package, Flipchip Design, and Wirebonding Package Design, Thermal & Electrical modeling & Simulation, TRIZ member Cadence APD/SIP design tool instructor. Strong Authority of Cadence APD/SiP, Sigrity UPD/XtractIM, Power SI, Autocad, Ansys Ice chip/SI wave /Q3D/HFSS, CAM350, Mentor Xpedition, Valor NPI (DFM), Mentor L-Edit (WLP design)
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