Harsh Mehta

About Harsh Mehta

Proficient in Power, Rail, EM Analysis and Signal Integrity with Industry standard tool– Voltus, Redhawk, Redhawk-SC• In-depth knowledge & industry experience in power integrity and package co-sim analysis• Working knowledge of programming to independently develop automation and parsing scripts with shell, AWK, sed, TCL for various EDA tools• Working knowledge of floorplan, place, route and CTS flow.• Working knowledge of STA, timing closure and ECO methodology and tools.• Outstanding problem solving, documentation and communication skills• Proven expertise on providing excellent customer support, ability to work well within a team to ensure successful tapeout

Experience

1. Ic Design Engineer (Chip Power Integrity)

   Broadcom

   Sep 2023 — Present · Austin, TX, US

Education

• California State University

  Master of Science, Electrical Engineering

  2010 — 2012

• Gujarat University

  B.S, Electronics and Communication

  2005 — 2009

Skills

• Nc-Verilog
• Design Compiler
• Logic Design
• Xilinx
• Linux
• Tcl
• Virtex 4
• Computer Architecture
• Rtl Coding
• Clock Tree Synthesis
• Ncsim
• Cadence
• Unix Shell Scripting
• Simulations
• Physical Design
• Perl
• Static Timing Analysis
• Spartan 3e
• Simulation
• Verilog
• Asic
• Altera Quartus
• Debugging
• Floorplanning
• Mips