Hiteswar T K

About Hiteswar T K

To pursue a challenging career as a Layout Design Engineer working on state of the art Layout design techniques, new technologies and also be part of a progressive organization that gives scope to both enhance and use the best of my knowledge.My core competencies are:* Experience in using EDA tools namely Cadence Virtuoso, Assura, Synopsys Custom Compiler and IC Validator.* Understanding of Transistor theory, Digital/Logic Design, Circuit theory and CMOS fabrication Technologies.* Experience in working on technology nodes namely; 2nm, 3nm, 14nm, 16nm, 28nm, 90nm, 150nm, 180nm* Hands-on experience in Standard Cell and Analog layout design.* Hands-on experience in designing SRAM Memory blocks from Leaf cells to Top block including Precharge, Sense Amplifiers, Data I/O and Decoders (Pre, Row and Column).* Hands-on experience in performing various physical verification checks like DRC, LVS and Parasitic Extraction.* Understanding of device failure mechanisms such as Antenna Effect, Latch-Up, Electro Migration, ESD and other short channel effects/second order effects and their prevention techniques.* Familiarity in working with Linux environment and ability to script in Perl, Tcl and Basic SKILL.* Good social, verbal and written communication skills.

Experience

1. Mask Design Engineer

   NVIDIA

   Jun 2025 — Present · Bengaluru, IN

Education

• Jain (Deemed-to-be University)

  B.Tech, Electronics and Communications Engineering

  2016 — 2020

• Maharishi Vidya Mandir Senior Secondary School

  XII (CBSE), PCBM

  2015 — 2016

• RV-VLSI VLSI and Embedded Systems Design Center

  Post Graduate Advanced Diploma in ASIC Design - Full Custom Layout Design

• Maharishi Vidya Mandir Senior Secondary School

  X (CBSE)

  2013 — 2014