Hitarth Patel
Post Silicon Validation Engineer
- Role
- Design Engineer 2 at Cadence
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Engineer 2
Jul 2023 — Present · Bengaluru, IN
Education
Institute of Infrastructure Technology Research and Management (IITRAM)
Bachelor of Technology - BTech, Electrical engineering
2017 — 2021
Texas A&M University
MS CEEN, Computer Engineering
Indian Institute of Technology, Mandi
Master of Technology - MTech, VLSI
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