Hiren Patel
Staff Design Verification Engineer at Analog Devices | Ex-IBM | Ex- eInfochips
- Role
- Staff Design Verification Engineer at Analog Devices
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Hiren Patel
10+ years of experience in ASIC design verification (DV) across all levels (subsystem/SoC/FPGA/ASIC) demonstrating complete DV of multiple blocks in ASIC/SoC projects from planning to closureTECHNICAL SKILLS: • Programming Languages: Verilog, System Verilog, C, C++ • EDA Tools/Version control: VCS, Xcelium, Questasim, Modelsim, DVE, Verdi, Perforce, SVN, SOS, cleartool_n_gvp, Vmanager, Vplanner • Verification Methodologies: UVM, Fusion• Verification Approaches: Constrained Random Verification, Coverage Driven Verification, Assertion Based Verification • Protocols: AXI, AHB, APB, SPI, I2C, I3C, Ethernet 100G(PCS), ONFI• Scripting Languages: Perl, Shell• Debugging & analytical skills to visualize and test critical and potentially buggy scenarios• Ability to work well with local & cross-site team-members in different time zones• System-level knowledge of debug
Experience
Staff Design Verification Engineer
Nov 2024 — Present · Bengaluru, IN
Education
N.M.HIGH SCHOOL
H.S.C.
2006 — 2008
N.M.HIGH SCHOOL
S.S.C.
2006
U.V.PATEL COLLEGE OF ENGINEERING
Bachelor’s Degree, B.Tech(EC)
2008 — 2012
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