Hiranmayee Krishnaswamy Bharadwaj

About Hiranmayee Krishnaswamy Bharadwaj

I’m currently a Physical Design Engineer at Texas Instruments, working on advanced SoC…

Experience

1. Physical Design Engineer

   Texas Instruments

   Jun 2023 — Present · Dallas, TX, US

   Executed the complete Place and Route (PnR) flow from RTL to GDSII for high-performance processing blocks at lower technology nodes, including memory subsystems, navigator subsystems, networking IP’s and security accelerator units. Developed and validated chip level timing constraints and the critical path timing closure by developing the delay line recipe using TCL. Optimized PPA targets through developing the floorplan, conducting multibit flop experiments, implementing low power techniques,conducting area scrunch experiments, VT swaps, clock skew and RAM optimizations while maintaining performance requirements. Developed robust Perl scripts to automate the verification processes in the PD flow for the methodology team, including a user-friendlyinterface and error handling for faster and efficient debugging across the design team. Performed physical verification checks (LVS/DRC) and collaborated with the top-level design teams to resolve other signoff violations Implemented ECO’s to fix timing, noise, power integrity issues, EM and IR violations for design reliability and robustness