Hiranmai Batte
Design Verification Engineer at INTEL
- Role
- Verification Engineer at Intel
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Verification Engineer
Apr 2024 — Present · Santa Clara, CA, US
Education
Jawaharlal Nehru Technological University, Kakinada
Bachelor of Technology - BTech
2014 — 2018
San Jose State University
Master's degree
2022 — 2023
Kendriya Vidyalaya
Cbse
2003 — 2012
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