Hetali Patel
- Role
- Hardware Verification Engineer at MIPS
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Hardware Verification Engineer
Oct 2013 — Present
Skills
- Cacti
- Cadence Virtuoso Layout Editor
- Cadence Nc Sim
- Cadence Nc-Verilog
- Cadence Spectre
- Modelsim
- Soc
- Unix
- Verilog
- Ltspice
- Systemverilog
- Perl
- C/C++ Stl
- Cadence Virtuoso
- Vhdl
- Cadence Soc Encounter
- Computer Architecture
- Multisim
- Windows
- Synopsys Tools
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