Herbert Rivera-Sanchez

About Herbert Rivera-Sanchez

Principal Verification Engineer with over 25 years of experience in semiconductor design and advanced SoC verification. My work focuses on architecture-level verification of memory and interconnect systems, development of reusable modeling infrastructure, and solving complex large-scale simulation and debug challenges.I have deep experience in ARM AXI protocol behavior, proprietary on-chip fabrics, and coverage-driven UVM methodologies. I currently own and maintain widely used verification models supporting memory mesh architectures and serve as a technical resource for complex system-level debug across teams.Throughout my career, I have contributed to subsystem verification for security and boot flows, interconnect protocol translation, and methodology standardization across organizations. I also mentor engineers in verification practices and explore practical applications of AI-assisted workflows for improving verification productivity.

Experience

1. Principal Verification Engineer - Soc, Memory & Interconnect Verification

   Marvell Technology

   Mar 2021 — Present · Morrisville, NC, US

   Provide technical leadership for architecture-level verification of memory, interconnect, and subsystem designs in advanced packet processing and communications SoCs.• Own and maintain a widely used memory and access verification model (vKit) implementing a proprietary on-chip memory mesh and access control architecture• Verify large-scale instruction-driven memory traffic (500K+ transactions/run) including relaxed-order completion and protection rules• Identified multiple RTL defects during high-volume ordering and access-control validation• Developed custom transaction trace instrumentation enabling effective debug at low UVM verbosity, reducing log volume for large simulations• Key contributor to verification of a BOOTSS subsystem within a chiplet-based architecture, focusing on boot sequencing and security access/management• Verified ARM AXI protocol behavior (bursts, QoS, protection, user signals, ID-based ordering) and translation into a proprietary on-chip fabric• Serve as a cross-team technical resource for complex debug and verification infrastructure issues• Mentor engineers in UVM methodology, environment architecture, and debug practices• Presented internal demo on applying AI-assisted workflows to test planning, coverage analysis, refactoring, and spec-to-test tracing

Education

• North Carolina State University

  Master of Science, Electrical and Computer Engineering

  1987 — 1990

Skills

• Application-Specific Integrated Circuits (Asic)
• Functional Verification
• Debugging
• Fpga
• Asic
• Analysis
• Perl
• Embedded Systems
• Eda
• Verilog
• Tcl
• Systemverilog
• Soc
• Open Verification Methodology
• Semiconductors
• Cadence
• Ic
• System on a Chip (Soc)
• Architecture
• Specman
• Integration
• Rtl Design
• Architectures