Hemaprasad Paluru

About Hemaprasad Paluru

I am a dedicated VLSI professional working as a DFT Engineer at AMD with experience in pattern Generation using the Tessent TestKompress tool. Pattern Simulations chain, serial and parallel patterns. ATPG coverage debug. Simulation mismatches debug using the Synopsis Verdi tool. Done PERL automation to extract the required information from the files and formulated using XLSX sheet with proper coloring and did a few tasks using TCL to extract and verify the Non-toggling ports at the pattern generation time. Have good knowledge in Automotive grade faults, Timing Aware ATPG, Path delay testing, CellAware fault models, and JTAG, and have knowledge of System Verilog, Digital design, and Verilog.With a research-oriented mentality and strong reasoning skills, I approach challenges with an analytical mindset and constantly seek innovative solutions. I excel at managing my work, handling multiple tasks with precision and meeting deadlines. Additionally, my natural curiosity drives me to dig deep and uncover the root cause of any problem.While I have a strong work ethic, I am actively working on maintaining a healthy work-life balance and managing expectations. I recognize the importance of sustained productivity and personal well-being.I am eager to contribute my skills and determination to a dynamic VLSI role, where I can continue to learn, innovate, and collaborate effectively. With an unwavering commitment to excellence, I am confident in my ability to drive successful outcomes and make significant contributions to the organization.

Experience

1. Sr Silicon Design Engineer

   AMD

   Dec 2025 — Present

Education

• Rajiv Gandhi University of Knowledge Technologies, RKValley (RAC)

  PUC, MPC

• VIT_Vellore Institute of Technology

  Master of Technology - MTech, VLSI Design

  2023

• Rajiv Gandhi University of Knowledge Technologies, RKValley (RAC)

  Bachelor's degree, Electrical, Electronics and Communications Engineering

• Zilla Parishad High School

  Secondary