Hemant Rathee
Principal Application Engineer at Cadence Design Systems
- Role
- Principal Application Engineer at Cadence
- Location
- Fremont, CA, US
- LinkedIn followers
- 500 followers
About Hemant Rathee
Design Verification engineer with strong background in Gate Level Simulation (GLS) set-up and enhancement. Well versed in SDF Delay Simulations, RTL, Unit level/ Block level Verification, Full chip Verification and Post-Silicon Validation. Strong background in ASIC, Digital logic Design and Verification. In depth knowledge of debug tools and simulators as VCS, Questa-sim, Verdi and Debussy. Experience in the RTL, GLS (Gate level simulation) debug, Silicon Debug. Hands-on Verilog, System Verilog, C++, Assembly Language, Python.
Experience
Principal Application Engineer
Jun 2023 — Present · San Jose, CA, US
Education
University of Southern California
Master of Science, Electrical Engineering
2008 — 2010
Maharishi Dayanand University
Bachelor of Engineering, Electronics and Communication Engineering
2004 — 2008
Skills
- Verilog
- Systemverilog
- Modelsim
- Soc
- Integrated Circuit Design
- Microcontrollers
- Spice
- Asic
- Ic
- C++
- Primetime
- Unix
- Microchip Pic
- Cadence
- Analog
- Debugging
- Cadence Virtuoso
- Perl
- Functional Verification
- Simulations
- Teradyne Ig-Xl
- Vlsi
- Rtl Design
- Rtl Coding
- Vmm
- System on a Chip (Soc)
- Integrated Circuits (Ic)
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.