Hemanth Varma

About Hemanth Varma

Physical Design Engineer with 3+ years of industry experience at Capgemini, delivering…

Experience

1. Physical Design Engineer

   Capgemini

   Jul 2022 — Present

   Synthesis & Optimization: Worked on synthesis and design optimization, including clock gating insertion, register replication, and sequential merge techniques to enhance design efficiency.• Static Timing Analysis (STA): Debugged setup, hold, and crosstalk issues, ensuring proper timing closure and analyzing all timing paths (IN2REG, REG2REG, REG2OUT, IN2OUT).• Logic Equivalence Check (LEC): Verified mapping points, inserted cut points, and implemented required corrections using ECO methodologies.• Low Power Implementation: Created multiple power domains, added isolation cells, level shifters, and power ports/nets, and performed VCLP checks on synthesis netlists.• Physical Design Contributions: Assisted in floorplanning, power planning, placement, routing, and final timing closure.Tools Used: Synopsys DC Compiler, PrimeTime (PT Shell), ICC2, Cadence RTL Compiler, FM Shell, VCLP, Encounter.