Hemanth Kumar Yadav

About Hemanth Kumar Yadav

I am interested in working as a DFT Engineer to meet the needs of the industry.In-depth understanding of Design for Test (DFT) & proven experience with implementation, validation, and post-silicon debug for silicon test.Experience in HDL – Verilog, SV, VHDL & proficiency in TCL or any scripting language.Hands on experience in EDA Tools: ATPG, Compression, Scan Synthesis, Diagnostics, Simulation and Post Silicon bring-up. Familiarity with Tessent flows and methodologies is a definite plus.Excellent interpersonal communication skills and confidence in direct interactions with customers.You\'ve great problem solving approach with debugging skills.Possess passion to build and foster customer and peer relationships with a positive demeanor to achieve business success.Provide technical support on ATPG, SCAN, COMPRESSION & DIAGNOSIS solutions to customers using Tessent tools. As a technical specialist, understand DFT challenges and provide instruction to our customers and field personnel.Improve customer productivity through efficient tool usage. Providing hands-on assistance for DFT QoR improvement & debug would be part of daily routine.Work closely with R&D to isolate and fix tool bugs. Describe, recreate, and solve problems in close interactions with engineering.Lead and develop team members with hands-on technical capabilities. Play active role in developing tool trainings and creating technical content to improve knowledgebase.MBIST• Created custom algorithms to identify the faults for SLT rejected dies.• Worked on defining methodologies and implementing DFT architecture for SoCs.• Inserted MBIST logic at Block and Top level.• Methodologies changes into MBIST architecture to reduce TestTime with higher Tckspeedup.• Responsible for simulations at different stages(BTO/MTO) for both timing/Zero delay on both RTL and Gate level.SCAN• Worked on defining methodologies and implementing DFT architecture for SoC’s.• Generated pinmux logic for different test modes.• Resolved issues related to vmin and fmax and shmoo holes.ATPG• Generation of test patterns which includes, compressed patterns and At-Speed vectors.• Identified and analyzed areas of low fault coverage and suggested mechanisms to increase coverage. IJTAG• Ijtag implementation for controlling blocks with SIB.• Development of ICL and PDL according to the test case.• Bscan implementation and verification for SoC level.

Experience

1. Application Engineer

   Siemens

   Jul 2017 — Present · Hyderabad, IN

   RTL Design Verification Engineer

Education

• JNTU Anantapur

  Bachelor's degree, EEE

  2006 — 2010

• School of Electrical Engineering

  Master of Technology - MTech, Power electronics and Electrical drives

  2011 — 2013

• Electrical and Electronics Engineering

  Masters in Electrical

• Sri Venkateswara childrens High School

  10 th standard, SSC

  1995 — 2004