Hemangi Deshmukh
Design & Verification Engg.
- Role
- Senior Silicon Design Engineer at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Hemangi Deshmukh
Experienced Design & Verification Engineer with a demonstrated history of working in the VLSI domain,having knowledge of Verilog, System verilog, UVM,VHDL,C. Strong engineering professional with a Master of Technology (M.Tech.) focused in vlsi design from Rajiv Gandhi Proudyogiki Vishwavidyalaya.
Experience
Senior Silicon Design Engineer
Jul 2024 — Present · Hyderabad, IN
Education
Rajiv Gandhi Prodyogiki Vishwavidyalaya
Master of Engineering - MEng
2010 — 2013
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.