Hema Latha
Sr. silicon design engineer specializing in Universal Verification Methodology (UVM)
- Role
- Sr Silicon Design Engineer at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Hema Latha
Expertise in ASIC verification and Universal Verification Methodology (UVM) to enhance silicon design processes. My role as a Senior Silicon Design Engineer involves developing robust verification environments that ensure product reliability and performance.Previously at Capgemini Engineering, I honed my skills in assertion-based verification, contributing to our success in ASIC design verification. My commitment to precision and innovation drives me to continuously seek out new methodologies and improvements in the field of silicon engineering.
Experience
Sr Silicon Design Engineer
Aug 2022 — Present · Hyderabad, IN
Hyderabad, Telangana, India
Education
Gayatri Vidya Parishad College of Engineering for Women, Madhurawada
Bachelor of Technology (B.Tech.)
2014 — 2017
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.