Hasan Taufique

About Hasan Taufique

Senior Principal Engineer with a demonstrated history of working in SRAM & Register file…

Experience

1. Senior Principal Engineer Masters

   Broadcom

   Oct 2014 — Present

   Memory Compiler Lead - 3nm multiport compiler Lead - architecture, design, PPA, characterization, design for yield and all aspect of verification to silicon validation. 5nm double pump compiler design- architecture & design solutions for PPA, characterization and margin analysis. 7nm double-pumped multi-port RF for high speed network applications. Developed architecture/ design for meeting PPA, compiler environment setup, characterization, final timing delivery to the customers & margin fixes across PVT and compiler range. Led 2R-2W multi-port single-pump compiler development with ownership of design, characterization and final view delivery to the customers. Achieved fully functional silicon in 7nm design that exceeded power-performance targets. Taped out 7nm SRAM test chip Lead- designed novel structures for silicon validation and VMIN analysis. Lead development of 7nm register-file/ multi-port compiler. Proficiency with RF, multi-port and SRAM design/ architecture, variation analysis, macro physical build, custom bit cell layout, characterization, margin, EM/IR, QA and compiler release.

Skills

• Memory Compiler
• Verilog
• Project Management
• Characterization
• Asic
• Physical Design
• Cadence Virtuoso
• Rom Design
• Design Management
• Static Timing Analysis
• Atom L2 Cache
• Soc
• Digital Circuit Design
• Perl Script
• Register-File
• Sram
• Low-Power Design
• Cache Design