Harshith Kameswara Sai Nittala
Sr Silicon Design Engineer @AMD
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WORK HISTORY
Sr Silicon Design Engineer @AMD
EDUCATION
Vellore Institute of Technology
Bachelor of Technology - BTech, ECE
Ira A. Fulton Schools of Engineering at Arizona State University
Master's degree, Electrical Engineering VLSI
ABOUT HARSHITH KAMESWARA SAI NITTALA
Working as an Physical Design Engineer in SerDes PD, IP design team at AMD, Santa Clara.Skills:Strong foundation in Digital design conceptsFamiliar with the architecture circuit co-optimization techniques (Co-design methodology).Good understanding of Physical design flow(RTL to GDSII), STA, APR concepts.Scripting and Automation using PERL and TCLEDA tool experience:Physical design, HSPICE simulations: Cadence Virtuoso, Cadence Innovus, HSPICE, Starrc, Synopsys Design Compiler, Xilinx Vivado, Matlab HDL flow advisor, Synopsys Primetime, gem5.
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