Harshita Sharma
SOC Logic Design Engineer
- Role
- Soc Logic Design Engineer at Intel
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Harshita Sharma
Skills : Digital Electronics, Verilog, System Verilog, Universal Verification Methodology.Tools : Questa Sim – Mentor Graphics, Riviera Pro – Aldec, ISE – Xilinx, Modelsim, Cadence VirtuosoI am interested in Semiconductors since i read about it in my physics book of high school. This interest lead me to do my Bachelor\'s and Master\'s degree in Electronics and Communication Engineering.My biggest achievement is getting a gold medal in my post graduation. My curiosity in world of transistors led me to do my M.tech thesis in field of VLSI about how we can reduce the power dissipation of various adders using body biasing techniques. This gave me a breakthrough to learn more about CMOS and its design techniques.Trained front end VLSI Engineer from Maven -Silicon, Bangalore. Worked as aRTL Design Engineer at Chipspirit Technologies Pvt. Ltd. for 3 years 2 months.Currently working as Soc Logic Design engineer in Intel corporation.
Experience
Soc Logic Design Engineer
Apr 2024 — Present · Hyderabad, IN
Education
Poornima Institute of Engineering & Technology
Bachelor of Technology - BTech
2012 — 2016
Sant Longowal Institute of Engineering and Technology
Masters of technology
2017 — 2019
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.