Harshit Makwana

Lead Design Engineer at Cadence | Ex. Samsung | IIT BOMBAY | Gold Medalist (🏅)

Role
Lead Design Engineer at Cadence
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers

About Harshit Makwana

Extensive experience in Verilog/SystemVerilog RTL coding, function/performance simulation…

Experience

  1. Lead Design Engineer

    Cadence

    Oct 2023 — Present · Bengaluru, IN

    GDDR PHY IP Design

Education

  • Indian Institute of Technology, Bombay

    Master of Technology - MTech, Electronic system

    2017 — 2020

  • L.D. College of Engineering

    Bachelor’s Degree, Electronics and Communications Engineering

    2014 — 2017

  • Government Polytechnic, ahmedabad

    Diploma, Electronics and Communications Engineering

    2011 — 2014

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Harshit Makwana — Lead Design Engineer at Cadence in Bengaluru, KA, IN | Unifers