Harshit Dhakad

Experience

1. Principal Engineer

   Intel

   Jul 2025 — Present · Bengaluru, IN

   Leading ESD development and enablement for products in external foundry technology • Key driver for ESD & LU implementation in product designs and pre-Si ESD verification sign-off across numerous technologies and products / IPs / test chips • Providing guidance and solutions on ESD target definition, conducts risk assessments for ESD LU at various chip/IP development milestones• Developing and implementing ESD custom solutions for RF, High Speed, and other interfaces, e.g. STEP, WIFI RX/TX, UCIe • Hosting the Technology ESD Working Groups and offering ESD training and guidance to the design community for optimized and efficient ESD protection. Transferring know-how and experience between projects. • Driving improvements of ESD and Latch-Up tool flows with ESD EDA vendors (Siemens, Synopsys.) and external foundries. Formulating new design checks based on ESD learnings.• Supporting failure analysis and post-Si debugging and closing the loop to pre-Si development, hence, covering various ESD topics across the whole product life cycle. • Developing, analyzing and driving ESD and Latch-Up test-chips, including TLP/VFTLP/UFTLP measurements and ESD model hardware correlation.

Education

• Government Engineering College Ujjain

  B.E., Electronics and Telecommunication

  1999 — 2003

• Indian Institute of Technology, Delhi

  M.Tech, Integrated Electronic Circuits

  2003 — 2005

• St. Thomas School, Mandsaur

  PCME

  1984 — 1998

Skills

• Analog
• Vlsi
• Very-Large-Scale Integration (Vlsi)
• Testing
• System on a Chip (Soc)
• Application-Specific Integrated Circuits (Asic)
• Microprocessors
• Mixed Signal
• Ic
• Cmos
• Asic
• Soc
• Eda
• Physical Design
• Esd Control
• Cadence Virtuoso
• Semiconductors
• Perc
• Esd Protection Circuit Design
• Debugging