Harsh Garg

About Harsh Garg

I am an experienced design and verification engineer who has worked on design of various complex NPU & CPU subsystems in Qualcomm and SoCs in Digital Networking group of Freescale. Exposed to all “cradle to grave” project development stages including definition, design, verification, validation and testing. Supported the validation and test team on SoCs getting a complete view on the cycle of SoCs. In Design, I have led the design of CPU subsystem for value tier MSMs and MDMs. I am well versed with all the design related microarchitecture and design flows from PLDRC, CDC, CLP to Synth. In verification, I have worked on the brain of SoC ( COP - Common On chip Processor ), Trust Architecture of Freescale SoCs and USB 2.0 verification.My strong suites are: 9 years of work experience in CPU subsystem design team of Qualcomm Inc. working across MDMs, MSMs to Compute chips spanning across v7 to v9 ARM architecture. Worked closely with various stakeholders across architecture, DV, synthesis, PD, SW, validation and customer support to deliver a industry leading CPUSS design with special focus on low power design in Snapdragon chipsets. Strong knowledge and experience with all RTL related flows - Lint, CDC, CLP etc. Working knowledge and understanding of QCOM SoC architecture. 4 years work experience in SoC verification team of Freescale Semiconductor working across Digital Networking products. Worked closely with Architects and RTL designers to develop a verification strategy and verify functional correctness of different modules in Soc @ Freescale Knowledge of industry standard interfaces, good understanding of SoC architecture and verification flow Exposure to design and verification tools (VCS or equivalent simulation tools ) Knowledge in protocols such as AXI,AHB, APB etc. Strong debugging and problem solving skills Strong interpersonal, communication and management skills. I am always ready to grasp and learn something new.Specialties- Verification improvements Methodology Development e.g. XPROP, Low Power verification using UPF- Root Cause Analysis of debugs on validation and test failures - Programming Languages: Verilog, System Verilog, C- Design Tools : Lint (Spyglass), 0in (CDC), Conformal Low Power- Simulation Tools : VCS, Verdi, Modelsim,IUS- Waveform Debuggers: DVE, nWave- Scripting Languages: Perl, Python

Experience

1. Senior Staff Engineer Manager

   Qualcomm

   May 2025 — Present · Noida, IN

   Leading a team to deliver AI subsystems with frontend ownership of design and verification

Education

• Guru Gobind Singh Indraprastha University

  B.tech, Electronics & Communication

  2007 — 2011

Skills

• Functional Verification
• Verilog
• Systemverilog
• Usb
• Debugging
• Integrated Circuit Design
• Low-Power Design
• Application-Specific Integrated Circuits (Asic)
• Very-Large-Scale Integration (Vlsi)
• Vhdl
• Simulations
• Perl
• Embedded Systems
• Cmos
• C
• Vlsi
• Semiconductors
• Soc
• Ic
• Rtl Design
• System on a Chip (Soc)
• Asic