Harshdeep Verma
Staff Engineer @ Synopsys
- Role
- Staff Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Harshdeep Verma
Dedicated and self motivated Semiconductor professional- 6+ years of experience in Design Verification- Expertise in functional verification using System Verilog and UVM- Experienced in test plan creation and test case writing in SV/UVM- Sound knowledge of Ethernet and UCIe protocols- Sound knowledge of security protocols like MACsec and IPsec- Skilled in Verilog, System-Verilog, UVM, C, Linux, Perforce, Git, Verdi, SimVision, V-manager- Skilled in efficiently handling customer support tickets- Independently authored and presented technical paper titled \"Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY\" in DVCon Taiwan 2023- Successfully filed US patent titled \"Low-Latency Timestamping of Transmissions at Physical Layer of Communication Devices and Systems\"- Excellent verbal communication and user interaction skills.
Experience
Staff Engineer
May 2025 — Present · Bengaluru, IN
Education
YMCA University of Science & Technology
Bachelor of Technology (B.Tech.), Electronics Instrumentation and Control Engineering
2013 — 2017
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