Harsha Vardhan Vudumula

About Harsha Vardhan Vudumula

Graduated from The University of Texas at Dallas, TX, USA.• Highly motivated research scholar at Hyderabad having more than 5+ years of academic and research experience in the field of digital ASIC and FPGA• Develop and execute assertion-based verification plans for critical IP blocks• Develop test plans and execute tests for the IP verification – TB Development• Integrated 3rd party IPs to the TB esp Synopsys IPs• Knowledge in developing UVM testcases to ensure maximum coverage, fluent in SystemVerilog based verification• Working knowledge of on chip interconnect protocols APB and AHB• Defined and developed capabilities to enable acceleration of RTL and improve emulation/FPGA model reusability across SoC• Proven knowledge in circuit design and optimization across a diversity of circuit types for performance, power, and area onCMOS Technology• Fluent in C based module level hardware modelling• Scripting experience in Perl-Contact Details-Phone:+91••••••••58Email: v••••••••@gmail.com

Experience

1. Sr Silicon Design Engineer

   AMD

   Jul 2024 — Present · Hyderabad, IN

Education

• Amrita Vishwa Vidyapeetham

  Bachelor of Technology (BTech)

  2010 — 2014

• The University of Texas at Dallas

  Master’s Degree

  2016 — 2017

• Kendriya Vidyalaya

  Junior High/Intermediate/Middle School Education and Teaching

  1998 — 2008

• International Institute of Information Technology Hyderabad (IIITH)

  Doctor of Philosophy - PhD (Part Time)

  2018 — 2022