Harsha Sriramagiri

About Harsha Sriramagiri

Harsha is the post silicon power and performance validation lead for next generation Graphics IP. His roles include* Collaborate with architects on new features and develop test-plan at both IP and system level.* Engage with software teams to develop required tools and flows to improve validation efficiency.* Execute post-silicon content on emulation and debug any performance issues before tape-out.* Cross collaborate with multiple teams such as driver, application developers, hardware designers and architects on debugs.* Performance at TDP, which involves analyzing v-f curves of parts and debug performance losses that may occur due to in-efficient power distribution in the SoC.* Experience in working with DAQ and hands-on with new Silicon.* Develop automation frameworks to improve efficiency and scalability, mainly in python.Prior to this role, Harsha was a hardware design engineer for 7 years in the Intel Graphics Division. His role was:* Design and validation of next generation Media IP. This involved developing test-bench and writing up test-plans.* Collaborate with back-end teams, understand layout flows and optimizing design for better timing.* Engage with post-silicon and driver teams on any silicon issues.* Engage with architects and contribute to architectural changes by challenging the status quo.

Experience

1. Senior Systems Performance Engineer

   NVIDIA

   Jun 2021 — Present · Santa Clara, CA, US

   Responsible for developing system level power/performance features for graphics and compute chips. Work closely with SW/ASIC/Silicon team, review power/perf data, identify bottlenecks and implement features to improve perf/W and perf/$

Education

• Anna University Chennai

  Bachelors, Electrical and Electronic Engineering

  2003 — 2007

• The Ohio State University

  Masters, Electrical and Computer Engineering

  2007 — 2009

Skills

• Matlab
• Modelsim
• Virtuoso
• Functional Verification
• Integrated Circuit Design
• Xilinx
• Systemverilog
• Debugging
• Rtl Design
• Cmos
• Perl
• Logic Design
• Code Coverage
• C++
• Cadence Virtuoso
• Performance Analysis
• Cadence
• Computer Architecture
• Verilog
• Fpga
• Asic
• C
• Vlsi
• Spectrum Analyzer
• Static Timing Analysis
• Synopsys Tools