Harshan Kumar

About Harshan Kumar

I am a 2025 graduate with a strong interest in VLSI Physical Design, skilled in the complete RTL-to-GDSII flow.Completed training at VLSI Guru where I gained hands-on experience in EDA tools {Synopsys}. Projects CompletedSynopnex28 → Implemented full RTL-to-GDSII flow in a Block level module, including floorplanning, placement, CTS, routing, and timing closure.ChipTop → A basic Physical Design Flow implementation.[PnR] Key Skills Floorplanning & Power Planning (ICC2) Placement, CTS & Routing (ICC2) Timing Closure & Signoff (Primetime) Physical Verification (DRC/LVS)I am passionate about solving timing, power, and congestion challenges in chip design and looking forward to contributing as a Physical Design Engineer.

Experience

1. Physical Design Engineer Traine

   Vlsiguru Training Institute

   Feb 2025 — Present · Bengaluru, IN

   Underwent hands-on training on complete physical design flow using industry-standard tools. Implemented floor planning, placement, clock tree synthesis [CTS],routing, and generation of GDSII for a sample SoC block. Performed a static timing analysis [STA] using Synopsys Prime Time to verify timing closure. Automated repetitive tasks using Tcl scripting and basic shell commands. Gained exposure to EDA tools: Synopsys Design Compiler, ICC2, PrimeTime.

Education

• Devineni Venkata Ramana & Dr. Hima Sekhar MIC College of Technology

  Bachelor of Technology - BTech, Electronics and Communications Engineering