Harshal Kothari

About Harshal Kothari

System on Chip (SoC) Design Verification Senior Staff Engineer with 8+ years experience working on wide range of ASICs on latest advanced technology nodes: Application Processors, Mobile Co-processors, Automotive, ADAS, XR (AR/VR/MR), HPC 3DIC and AI/ML Accelerator Data Center chiplet based 2.5DIC SoCs at Foundry Design Services (Hardware) division at Samsung Semiconductor.Expertise in SoC boot, low power management, ARM/RISC-V based CPUs and MCUs, high speed die-to-die UCIe, Storage (UFS), MIPI CSI, system control and peripheral IPs, in-system functional safety (MBIST/LBIST) and security over complete cycle of Pre-Silicon SoC Design Verification- specification and architecture to RTL, Power Aware RTL with UPF, Unit Delay and Timing (SDF) Gate Level Simulations (GLS) and Post PnR PGnet Power Aware GLS.Proficient in SystemVerilog (SV), Universal Verification Methodology (UVM), Verilog, C, Python, Perl and TCL.Skilled in EDA simulator tools like Cadence Xcelium (NCSim), IMC, vManager, Synopsys VCS and debugging tools like Verdi, Verisium, Simvision.Actively contributing to cutting edge ASIC/Silicon ecosystem R&D with 15+ paper publications and 5 Best Paper and 2 Best Poster wins across industry leading VLSI technical and internal conferences.Electronics major from National Institute of Technology, Warangal with a keen interest in digital electronics and the current trends and innovations in semiconductor industry.

Experience

1. Senior Staff Engineer

   Samsung Semiconductor

   Mar 2024 — Present · Bengaluru, IN

Education

• National Institute of Technology Warangal

  BTech - Bachelor of Technology, Electrical, Electronics and Communications Engineering

  2013 — 2017