Harshal Dhage

About Harshal Dhage

I am a recent B.Tech Graduate in Electronics and Communication Engineering from Deogiri Institute of Engineering and Management Studies (DIEMS), where I graduated with a First Class degree. I am currently seeking Graduate/Entry-level roles in RTL Design, ASIC Design, or FPGA Prototyping.I became passionate about RTL Design and CPU Microarchitecture during my internship at NIELIT, where I architected a 5-stage pipelined RISC-V processor from scratch. There is a unique thrill in seeing complex logic come to life on an FPGA, like when I successfully met timing at 100 MHz on an AMD Artix-7 for my RISC-V SoC. My experience at FOSSEE, IIT Bombay, further solidified this passion as I developed over 12 RTL modules with IP and achieved 95% functional coverage through rigorous verification.I am driven by the challenge of optimizing hardware for high performance and am eager to contribute to the next generation of silicon chips.

Experience

1. Vlsi Design Intern

   Nielit

   Aug 2025 — Present · Aurangabad, IN

   Architected a 5-stage pipelined RISC-V microarchitecture using Verilog, improving throughput by 5x. Integrated AXI4-Lite bus interconnects with memory-mapped I/O for a RISC-V SoC- Successfully implemented the core on an AMD Artix-7 FPGA, achieving 0.8 IPC and meeting timing at 100 MHz

Education

• Deogiri Institute of Engineering and Management Studies, Aurangabad

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering