Harsha Ambardekar
- Role
- Senior Asic Design Engineer at NVIDIA
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Harsha Ambardekar
Interested in Cache and Memory System Hierarchy Design for multi core processors
Experience
Senior Asic Design Engineer
Oct 2021 — Present
Education
Sathaye College
High School, Science
2007 — 2009
Sadhana Vidyalaya
Completed school, Science
1996 — 2007
Carnegie Mellon University
Master's Degree, Electrical and Electronics Engineering
2014 — 2015
Vidyalankar Institute of Technology, Mumbai
Bachelor of engineering, Electronics Engineering
2010 — 2014
Skills
- Microsoft Office
- Programming
- Vlsi
- Verilog
- Matlab
- Rtl Design
- Perl
- Xilinx Ise
- Java Applets
- Microsoft Powerpoint
- Python
- Digital Circuit Design
- Xilinx
- Teaching
- Static Timing Analysis
- Linux
- Cache Coherency
- Labview
- Circuit Design
- Public Speaking
- Creative Writing
- Memory Management
- C
- Event Management
- Modelsim
- Computer Hardware
- Multisim
- Microprocessors
- Electronics
- Freelance Writing
- Application-Specific Integrated Circuits (Asic)
- Pspice
- Memory Controllers
- C++
- Algorithms
- Computer Architecture
- Vhdl
- Debate
- Integrated Circuit Design
- Keil
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