Harsha Vardhan A.
Staff Engineer at Arm
- Role
- Staff Engineer at Arm
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Harsha Vardhan A.
12+ years of experience in CPU Design and verification at unit, top and system level with expertise in:* Armv8-A, Armv9-A architecture* RTL design* UVM and SystemVerilog TB development* Formal Property Verification* Low Power Verification (power aware)Languages:Software Programming: CHDL: Verilog Hardware Verification: SystemVerilog, UVM Scripting: Perl, TCL, PythonAssertion: PSL, SVAEDA Tools: JasperGold, Cadence\'s Incsive Formal Verifier (IFV), Synopsys\'s VCS, Verdi, Cadence\'s Virtuoso Schematic and Layout Editor, Synopsys\'s DC Ultra, Synopsys\'s Formality Ultra, Synopsys\'s TetraMAX
Experience
Staff Engineer
Apr 2022 — Present · Austin, TX, US
Education
University of Minnesota
Master Of Sceince, Electrical Engineering
Birla Institute of Technology and Science, Pilani
BE (Hons.) Electrical and Electronics Engineering
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.