Harsh Soni
Senior SoC Verification Engineer @ NVIDIA | Pre Silicon, FPGA, Emulation & Post-Silicon Validation | AMBA (AXI/CHI)
- Role
- Sr Soc Verification Engineer at NVIDIA
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Harsh Soni
SoC Design Verification Engineer with 9+ years of experience spanning accelerated verification IP development, firmware engineering, FPGA/emulation validation, and post-silicon bring-up.At NVIDIA, I worked on firmware development in C++ to support Design Verification workflows, including test infrastructure bring-up, FPGA and emulation-based validation, post-silicon debugging, and test plan implementation. I also have hands-on exposure to DFT concepts due to IP interactions within the verification flow.Previously at Cadence Design Systems, I developed high-performance Accelerated Verification IPs for AMBA protocols (AXI, CHI, AHB-Lite), working across architecture, implementation, customer debugging, and large-scale product re-architecture.
Experience
Sr Soc Verification Engineer
Jan 2024 — Present · Bengaluru, IN
Education
JECRC University
Bachelor of Technology (B.Tech.), Electronics and Communication Engineering
2012 — 2016
Skills
- Verilog
- System Verilog
- C
- C++
- Testing
- Product Analysis
- Technical Analysis
- Microsoft Office
- Microsoft Word
- Powerpoint
- Embedded Systems
- Vlsi
- Qemu
- Red Hat Linux
- Ethernet
- Leadership
- Teamwork
- Microsoft Excel
- Matlab
- Rtl Design
- Electronics Hardware Design
- Digital Electronics
- Python
- Programming
- Linux
- Microsoft Powerpoint
- Model Sim
- Xilinx Ise
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