Harsh Patel
DFx/DFT Sr Engineer at Synopsys Inc | Ex-Insemi Technologies |
- Role
- Sr Engineer at Synopsys Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
Experience
Sr Engineer
Nov 2024 — Present
High-Speed I/O Access Test (HSAT)-Worked on High-Speed I/O Access Test (HSAT) development and validation across three HSAT design versions-Performed SpyGlass checks, logic synthesis, DFT scan insertion, Formal Equivalence Checking (Formality), ATPG, and zero-delay simulations to ensure HSAT design correctness and test readiness-Analyzed test coverage reports to identify major coverage drop points and implemented improvements in controllability and observability to enhance HSAT testability-Improved overall HSAT test coverage by modifying test logic and access paths based on coverage analysis-Developed a comprehensive HSAT test plan to validate all supported features, configurations, and operational modes-Executed HSAT in functional mode using ALE, generating protocol-compliant packets to test the DUT across multiple configurations-Led the bring-up of the FC flow for HSAT and validated correct integration and execution-Set up and executed ALE regression flows for robust HSAT validation and to identify functional and tool-related limitations in ALE-Integrated and validated HSAT with SF and SEQ flows (HSAT + SF + SEQ) to ensure correct sequencing and interoperability across test modes-Debugged functional, coverage, and integration issues to improve robustness, reliability, and reusability of the HSAT solution-PVT (Process, Voltage, Temperature) Controller IP validation on different configs -Performed SpyGlass RTL checks to identify and resolve lint, CDC, and structural issues-Executed logic synthesis to generate gate-level netlists meeting functional and design constraints-Implemented DFT scan insertion and verified scan integrity and test readiness-Generated and analyzed ATPG patterns to achieve required fault coverage for the PVT controller logic-Performed zero-delay gate-level simulations to validate logical correctness after synthesis and DFT insertion.
Education
BITS Pilani Work Integrated Learning Programmes
Master of Technology - MTech, microelectronics
Swami Sacchidanand Polytechnic college,Visnagar 650
Diploma, electrical engineering
2012 — 2015
Pandit Deendayal Energy University
Bachelor of Technology - BTech, Electrical and Electronics Engineering
2015 — 2018
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