Harsh Chilwal
Scientist/Distinguished Engineer at Synopsys Inc
- Role
- Scientist at Synopsys Inc
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
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About Harsh Chilwal
Specialties: VLSI Design and Verification.Low Power design and VerificationUnified Power Format (UPF)Common Power Format (CPF)Co-Author of ArchPro Power Format (APF)Assertions and Low PowerSystem Verilog and UVMC/C++, Haskell
Experience
Scientist
Mar 2024 — Present · Sunnyvale, CA, US
Education
Indian Institute of Technology, Kanpur
Bachelors of Technology, Electrical Engineering
1997 — 2001
St. Joseph's College, Nainital, India
ICSE
1984 — 1994
Skills
- Ic
- Vlsi
- Tcl
- Embedded Systems
- Eda
- System on a Chip (Soc)
- Verilog
- Fpga
- Soc
- Asic
- Low-Power Design
- Very-Large-Scale Integration (Vlsi)
- Rtl Design
- Field-Programmable Gate Arrays (Fpga)
- Veritas Cluster Server
- Debugging
- Formal Verification
- Systemverilog
- Integrated Circuits (Ic)
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