Harrish Mahanthesh
Senior Verification Engineer @ Cadence design systems.
- Role
- Sr Principal Product Engineer at Cadence
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Harrish Mahanthesh
As a Senior Verification Engineer at Synopsys, I leverage my 12+ years of extensive ASIC Design and Verification experience to deliver high-quality solutions for our customers. I have a strong technical and problem-solving capability, as well as excellent interpersonal skills to collaborate with internal and external stakeholders.My core competencies include developing and executing verification plans, test cases, and environments using System Verilog (UVM), Constrained Driven Verification, and VIP development. I also have experience in formal verification using Jaspergold and VC-formal, as well as scripting languages such as Perl, Python, and Shell. Some of the protocols I have worked on SoC level 802.3 Ethernet Standard and PCIe verification, Additionally,I have worked on AMBA, I2C, UART, and SPI protocols. I have worked on ARM based processors like Cortex M7 and A75. My mission is to ensure the functional and code coverage of various SoC with multiple interfaces and regression automation.
Experience
Sr Principal Product Engineer
Apr 2025 — Present · San Jose, CA, US
Education
Visvesvaraya Technological University
Bachelor of Engineering (B.E), Electronics and Communication
2005 — 2009
Visvesvaraya Technological University
M.Tech, Digital Electronics and communication
2009 — 2011
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