Harri

About Harri

ASIC Verification Engineer with 8+ years of experience :* Working in the DDR 5 protocol* Developed the test bench from the scratch and integrated the QUESTA VIP in the testbench for AXI4_Interconnect, AXI4_AHBLITE IP and AXI4_APB3 IP* Verification of AXI4 Interconnect, AXI4_AHBLITE IP and AXI4_APB3 IP using the QUESTA VIP* Understanding of Universal Asynchronous Receiver Transmitter (UART) specification.* Extracting the feature list and populating the scenarios for UART.* Understanding of I2C specification and populating the corner scenarios for I2C.* Understanding of 3GPP LTE Spec Cell Search and DL concepts* Understanding the design and software requirements to implement the same in verification.* Learning new technologies (LTE specific) and populating scenarios.* Developed and maintained a design verification environment for both ASIC and FPGA technologies* Development of the COSIM environment to qualify the Real time Software’s compatibility with RTL.* Verified the cell search modules using AXI, AHB and Z-turbo protocols* Verified most of the test cases using Randomization, Constraints and System verilog Assertion (SVA).* Implementation and verification of Low power features such as Power Shut-Off (PSO) with UPF and Clock Gating (CG).* Verification of other key features such as Master reset, Memory Sleep and Shutdown.* Verification of XSPI protocol with the semper memory model* Prepared design verification plan based on design specifications.* Part of a successful tape-outs in delivering consistent mobile broadband product* Understanding of USB2.0 Specification and debugging some of the Regression Failure Scenarios

Experience

1. Verification Team Lead

   Mobiveil Inc

   Mar 2023 — Present · Bengaluru, IN

Education

• Arasan Ganesan polytechnic college of engineering

  Diploma , Electrical, Electronics and Communications Engineering

  2011 — 2014

• Ramco Institute of Tecnology

  ECE, Electrical, Electronics and Communications Engineering

  2014 — 2017