Harmanpreet Kaur

About Harmanpreet Kaur

working on ATPG for intel core group. Lead the project and successfully WotWorking in ATPG for intel core group.Responsible for delivering GLS clean ATPG patterns meeting the coverage PoR for SSN based design.Worked on post silicon debug for ATPG. successfully completed the project from design phase till post silicon bring up.Identified and proposed design changes for improved test coverage and pattern count reduction.Experience with retargetting and diagnosis flowhands on Experience for writing timing constraints, sdf and on timing GLS.involved in mentoring 3 interns with DFT basics.Worked in Qualcomm as a DFT CAD engineerPresently exploring SSN scan architecture.Handling SSN scan insertion,DFT stitch for few design cores.Hands on experience in mbist insertion and pattern generation using Synopsys STAR memory testing solution (SMS). Leading the SMS flow across the sites as a single PoR. Works closely with EDA companies to implement new capabilities in the design.Worked on RTl sign off checks such as CDC and lint.Worked on Spyglass based clock tracing Hands on repair methodology to improve yield.Handled robust mbist insertion w.r.t to different clock and power domains.Derived various initiatives for MBIST test time and vector count optimizations.Familiar with EDT, ATPG, fault models and scan tracing.Familiar with shared bus architecture for teating memories.Proficient in sypglass, Synopsys verdi. vcs, Yield accelerator, SMS embedit toolProficient in Verilog, TCL, Perl, shell scripting.6 months internship experience in NXP Semiconductors.Worked in the SoC arch and FE integration.Experience with SoC integration and RTL generation flow. Hands on experience for Semiconductor Reuse Standard and clock and reset architecture used in the SoC. Architectural understanding and done integration of ADC, temperature sensor, Serial Peripheral Interface in the SoC. Familiar with RTL sign off checks: LINT, CDC, RDC. Handled LINT checks on ongoing project.

Experience

1. Senior Dft Engineer

   Intel

   Jul 2022 — Present · Bengaluru, IN

   working on ATPG for intel core group. Lead the project and successfully delivered GLS clean ATPG patterns meeting the coverage PoR for SSN based design.experience in post silicon debug. successfully completed the project from design phase till post silicon bring up.Identified and proposed design changes for improved test coverage and pattern count reduction.Experience with retargetting and diagnosis flowhands on Experience for writing timing constraints, sdf and timing GLS.involved in mentoring 3 interns with DFT basics.

Education

• Thapar Institute of Engineering & Technology

  Bachelor of Engineering, Electronics and communication

  2014 — 2018