Harisudhan Subramanian

About Harisudhan Subramanian

I am a Physical Design Engineer with 6+ years of experience delivering high-performance CPU implementations in advanced-node environments. My work focuses on backend convergence, including placement optimization, routing, CTS, timing closure, and power-aware optimization within hierarchical RTL-to-GDSII flows.I specialize in congestion-driven placement, timing closure, SI-aware cleanup, activity-based power optimization, and multi-Vt strategy tuning to achieve aggressive PPA targets. Having worked on multiple ARM Cortex-A CPU generations, I have developed a strong understanding of convergence challenges in large-scale hierarchical designs.With a foundation in both implementation and methodology, I leverage scripting and flow-level insights to improve efficiency, stability, and turnaround time across complex design environments.TECHNICAL SKILLSPhysical Design: RTL-to-GDSII Implementation, Macro placement, Hierarchical Design, Placement Optimization, Congestion & Routing Overflow Analysis, Clock Tree Synthesis, Setup/Hold Timing Closure, SI-Aware Optimization, Activity-Based Power Optimization, Multi-Vt Management, ECO Implementation, AnalysisDesign Tools: Cadence Innovus, Genus, Tempus, Cerebrus, Synopsys Design Compiler, IC Compiler II, PrimeTime.Programming Languages: TCL, Python, C, C++

Experience

1. Physical Design Engineer (Product Engineer)

   Cadence

   Oct 2019 — Present · Austin, TX, US

   Executed RTL-to-GDSII implementation of ARM Cortex-A CPU blocks using a top-down hierarchical methodology.• Performed placement optimization and congestion analysis, resolving routing hotspots to improve routing quality and timing stability.• Implemented and tuned Clock Tree Synthesis (CTS), optimizing skew and insertion delay across scenarios to balance setup and hold timing.• Drove setup and hold timing closure across multiple CPU generations, including SI-aware optimization, achieving >3.2 GHz targets under aggressive PPA constraints.• Applied activity-based power optimization and managed multi-Vt cell strategies within the implementation flow to improve power efficiency while maintaining timing convergence.• Optimized hierarchical timing budget allocation to eliminate over-constraint, reducing implementation turnaround time (TAT) by 10% while improving overall PPA.• Performed design space exploration using Cerebrus to optimize Power, Performance, and Area (PPA).• Developed TCL and Python automation scripts to analyze PNR databases, automate reporting, and accelerate debug cycles.• Collaborated with R&D to integrate improved implementation methodologies across projects, enhancing convergence and overall flow robustness.

Education

• The University of Texas at Dallas

  Master of Science - MS, Electrical Engineering

  2017 — 2019

• Anna University Chennai

  Bachelor of Engineering - BE, Electrical and Electronics Engineering

  2010 — 2014