Harishnaik K P
Lead Engineer @Tejas Networks
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WORK HISTORY
Lead Engineer @Tejas Networks
Bengaluru, IN
EDUCATION
GOVT POLYTECHNIC
DIPLOMA, Electronics and Communications Engineering
Annamalai University, Annamalainagar
Post Graduate Diploma, Business Administration
Sri Siddhartha Institute of Technology
Master of Technology (MTech), VLSI and Embedded Systems
Sri Jayachamarajendra College Of Engineering
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
B. M. S. College of Engineering
Doctor of Philosophy - PhD, VLSI Design and Testing
ABOUT HARISHNAIK K P
Presently working as a Lead Engineer R&D FPGA in Tejas Networks. R&D Work Experience:1. Design, Development, Implementation and Testing Of Encryption Equipments.2. RTL Designing using Verilog HDL.3. Familiar with Xilinx and Altera FPGA families.4. Familiar with Xilinx ISE, Vivado and Quartrus tools.5. Debugging using Chipscope analyser and Signal tap analyser.6. Static Timing Analysis.7. Cross Domain Crossing Checks.8. Experience in SDH/PDH interface (E1, E3, STM1 and STM4).9. Experience in Ethernet interface.10. Experience in GPIO, LVDS, UART, SPI and USB protocol.12. SOC Integration.13. Strong Knowledge in Digital Design.14. Strong Knowledge in Data Communication and Networking Elements.15. Experience in Interaction with customer, Vendor and govt officials.
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