Harish Kumar Polepalli
Layout Design Engineer at Google
- Role
- Layout and Automation Design Engineer at Google
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Harish Kumar Polepalli
Layout Designing on stdcell-I had worked on lower technologies-14nm on finfet(gf).28nm on CMOS technology(tsmc and gf).90nm on CMOS Technology (tsmc).Presently working on -22nm on FDX Technology (gf).Expertise on Physical Verification-DRC.LVS.DFM.PM.LEF Generation.Expertise on Stdcell Flops Design.Familiar with SVRF RuleDeck.Expertise on analysing on PPA(Power Performance Area).Familiar With EM(ElectroMigration).Good on Architecture Analysing on Technology.Excellent skill on analysing of Quality Analysis on Stdcell Layout Library.Good knowledge on tools-Calibre tool.Virtuoso tool.Abstract tool.Good skill on logic Analysis on combinations, Complex and sequential cells.Good Communication Skills.Scripting languages-Linux.C Language.Perl.TCL.Shell language on virtuoso tool.
Experience
Layout and Automation Design Engineer
Sep 2023 — Present · Bengaluru, IN
Education
IETE NEW DELHI
Bachelor's degree, Electronics and Communication Engineering
2015 — 2018
GOVERNMENT INSTITUTE OF ELECTRONICS IN A.P
Diploma, Embedded System on ECE.
2011 — 2014
Surya Public School
Ssc
2010 — 2011
BITS Pilani Work Integrated Learning Programmes
Master of Technology - MTech, Microelectronics
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