Harish Gurram
Manager, ASIC Physical Design at Synopsys Inc
- Role
- Manager Asic Physical Design at Synopsys Inc
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Harish Gurram
Working experience on technology nodes 4nm, 7nm, 14nm, 12nm, 22nm, 28nm, 45nm, 90nm, 180nm for various foundries. Good understanding and working experience on Fin-FET, FDSOI advanced process technologies. Working experience with Double Patterning and Self Aligned Double Patterning technologies Good knowledge on CMOS and Device Physics Good knowledge on Place & Route and Static Timing Analysis Working experience of STA vs SPICE correlations Working experience of developing Place & Route reference methodology flows for advanced process nodes Experience of working in Physical Verification at different hierarchical levels Good knowledge on Parasitic Extraction and Post Layout Simulations Working experience on Electromigration & IR Drop Analysis Familiar with Standard Cell Library development and Standard Cell Library views generation for Place & Route tools. Expert in Calibre SVRF code development and writing in rule decks Familiar with scripting of Shell, Perl, Tcl, Skill, Calibredrv Good experience in developing methodologies and flowsEDA Tools Known: Cadence Genus, Encounter/Innovus, Tempus Cadence QRC Cadence Spectre, Voltus/Voltus-FI Synopsys DC Compiler, IC Compiler – II, PrimeTime Synopsys StarRC Synopsys HSPICE Synopsys ICV Mentor Graphics Calibre DRC, Calibre LVS, Calibre PM Mentor Graphics Calibre XACT Ansys Totem
Experience
Manager Asic Physical Design
May 2022 — Present · Hyderabad, IN
Education
Govt. Institute Of Electronics Secundrabad
Special Diploma In Electronics, Industrial Electronics and Instrumentation Engineering
2009 — 2012
The Institute Of Electronics and Telecommunication Engineers
AMIETE, Electrical, Electronics and Communications Engineering
2012 — 2012
Huzurabad Public School
SSC
2004 — 2009
Skills
- Routing
- Simulations
- Verilog
- Post Layout Simulations
- Sadp
- Spice
- Physical Verification
- Pnr
- Fdsoi
- C
- Floorplanning
- Tcl
- Finfet
- Vlsi
- Double Patterning
- Parasitic Extraction
- High Capacity Power Ir/Em
- Soc
- Very-Large-Scale Integration (Vlsi)
- Matching
- Clock Tree Synthesis
- Place & Route
- Perl
- Eda
- Static Timing Analysis
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