Harish G

About Harish G

Physical Design Engineer with over 4 years of experience in advanced semiconductor design, specializing in cutting-edge 7nm and 3nm technology nodes. Demonstrated expertise in managing end-to-end ASIC design flow, including floor planning, power planning, placement, Clock Tree Synthesis (CTS), routing, and timing closure for complex chip designs with high macro counts and multi-clock domains. Proficient in resolving critical design challenges like congestion, setup/hold violations, Crosstalk, Electromigration, and IR Drop. Skilled in optimizing chip performance through advanced techniques like High Fan-Out Net Synthesis (HFNS), driver strength adjustments, and Engineering Change Orders (ECOs). Experienced in using industry-leading tools such as Synopsys ICC2, Cadence Innovus, Tempus, and PrimeTime to deliver high-performance designs while meeting stringent PPA and sign-off requirements. Adept at automating workflows with scripting (Tcl, Python) to enhance efficiency and accuracy in physical design processes.

Experience

1. Lead Engineer

   HCLTech

   May 2025 — Present

Education

• Vaagdevi College of Engineering

  Master's degree, VLSI

• Tirumala Engineering College

  B.Tech, Electrical, Electronics and Communications Engineering

  2010 — 2014