Harish Dangat

About Harish Dangat

Broad understanding and experience of Semiconductor Physical Design in Advanced Technologies, low power and high speed designs and flow development. Worked on 20+ tapeouts of Microprocessors, Multimedia Processors, Network Processors, Network Search Engine chips. Good understanding of semiconductor device physics, process technology, testing and reliability, Design for Test (DFM), Design for Manufacturing (DFM).Specialties: RTL to GDSII Flow, Low Power Design, Flow Development Synopsys Tools - IC Compiler, Astro, DC Compiler, DFT Compiler, Tetramax, HSPICE, StarRC, FormalityCadence Tools - Innovus, EDI, QRC, First Encounter, Silicon Ensemble, Virtuoso, Vampire Mentor Graphics - Calibre Physical Verification, TestKompress, MBist (Test and Repair), Scripting - Python, R, TCL, Perl, C-Shell, C, Pascal, FortranOther skills - Data Science, Machine Learning, Statistical Machine Learning

Experience

1. Technical Manager (Physical Design)

   台積電

   Aug 2014 — Present · San Jose, CA, US

   Physical Design of critical customer\'s projects on TSMC\'s 14A, 2nm, 3nm, 5nm, 7nm, and 10nm technology.Physical Design of ARM Cores in TSMC\'s Advanced Processes.Physical Implementation (RTL2GDS2) of A57, A53, A7 in 28nm, 16nm, and 7nm Technologies. Train and mentor junior team members. Benchmarking TSMC\'s different technologies and different libraries.

Education

• Savitribai Phule Pune University

  B.Sc., Physics

• Indian Institute of Technology, Bombay

  M. Tech., Micro-electronics

• The University of Texas at Austin

  Analog Integrated Circuit Design Course, Analog Integrated Circuit Design Course

• Savitribai Phule Pune University

  M.Sc., Electronic Science

Skills

• Soc
• Lvs
• Redhawk
• Hspice
• Spice
• C-Shell
• High Speed Design
• Memory Bist
• Clock Tree Synthesis
• Cmos
• Perl
• Physical Design
• Application-Specific Integrated Circuits (Asic)
• Verilog/Vcs
• Tcl
• Logic Equavalency Check
• Cadence (Innovus/Encounter)
• Synopsys Tools (Icc, Dc, Primetime, Starrc, Hspice)
• Awk
• Design for Test
• Tetramax
• System on a Chip (Soc)
• Place & Route
• Dft
• Low-Power Design
• Python (Numpy, Pandas, Seaborn)
• Semiconductors
• Physical Synthesis
• Scan and Atpg
• Low Power Design
• Timing Closure
• Ic Compiler
• Ddr3
• Asic
• Bist
• Calibre Drc, Lvs, Dfm
• Compilers
• First Encounter