Hariprasad T T
Engineer at Intel Corporation
- Role
- Circuit Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Hariprasad T T
VLSI Engineer with 20+ year experience in VLSI Industry, Expert in micro-architectural design and high-speed SERDES/MEMORY PHY. Led cross-functional teams in silicon bring-up and pioneered innovative clock distribution methods. Developed cutting-edge solutions for AMD\'s product lines, including adaptive clocking and digital frequency synthesizers. Extensive experience in STA/SSTA methodology and tool validation for high-performance semiconductor design.Specialties- Custom Digital Circuit Design for High-Performance & Low-Power- Jitter analysis for PLL wrapper / Frequency Synthesizer- Uncertainty Calculation for Clocking Circuits- MTBF Calculation for synchronizers- Signoff methodology implementation and deployment- PrimeTime & NanoTime- Power Analysis- Physical Design- DC/ICC2- Statistical Static Timing Analysis- STA /SSTA -able ESRAM compiler - Design Optimization- Timing Analysis- Statistical Spice Simulation - Corner & Statistical Characterization of std. cells & complex cells - OCV, AOCV, POCV- Matlab, Octave- Perl, Tcl, Shell, Python- High-Performance Multi-GHz Clock Distribution- Clocking techniques for Power/Performance- Power efficient clocking technique/clock tree optimization- Digital Frequency Synthesizer Design- Serializer / Deserializer- EMIR analysis- ESD analysis- Ultra Low Power Design- RTL- LEC-AMS / CO-SIM Worked on various technology nodes (130nm,90nm,65nm,45nm,40nm,32nm,28nm,20nm,16nm,14nm,7nm,5nm)
Experience
Circuit Design Engineer
Aug 2019 — Present · Bengaluru, IN
GDDR7 micro architecture from scratch to silicon.Silicon Bring up and Characterization of GDDR7 IP with 3 GDDR7 memory vendors.UCIE_Gen2 Path Finding, PDN optimization / Channel Response identificationDie 2 Die interface (FOVEROS)Subthreshold Sequential Cell Design
Education
Cochin University of Science and Technology
M Tech, Electronics
2004 — 2006
Govt. Arts & Science College ,Kozhikode
Pre Degree, Science Group
1996 — 1998
Cochin University of Science and Technology
M Sc, Electronics
2002 — 2004
College Of Applied Science
B.Sc., Electronics
1996 — 2002
Sree Rama Krishna Mission,Kozhikode,Kerala
High School
1993 — 1996
Skills
- Shell Scripting
- Soc
- Linux
- Sram
- Simulation
- Hsim
- Clock Distribution
- System on a Chip (Soc)
- Vlsi
- Cmos
- Low Power Design
- Timing Closure
- Application-Specific Integrated Circuits (Asic)
- Vlsi Cad
- Ptsi
- Clocking
- Jitter
- Circuit Simulation
- Signal Integrity
- Ic
- Characterization
- Design Optimization
- Perl
- Eda
- Static Timing Analysis
- Rtl Design
- Ip Design
- Matlab
- Low-Power Design
- Debugging
- Very-Large-Scale Integration (Vlsi)
- Verilog
- Asic
- Semiconductors
- Circuit Analysis
- Python
- Lec
- Integrated Circuit Design
- Microprocessors
- Tcl
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.