Haripradhap A
RTL Design | Digital Electronics | Verification | UVM | SPI | Python Scripting | Spyglass Lint | Design Compiler | system verilog | linux | verilog
- Role
- Rtl Design Engineer at Maven Silicon
- Location
- Dharmapuri, TN, IN
- LinkedIn followers
- 500 followers
About Haripradhap A
Enthusiastic and detail-oriented Electronics Engineering graduate (2025 pass-out) with a strong foundation in VLSI design, currently pursuing an advanced course in ASIC Design and Verification at Maven Silicon Pvt. Ltd. Skilled in digital design concepts, Verilog/SystemVerilog, RTL coding, and verification methodologies (UVM). Possess hands-on experience in writing testbenches, functional simulations, and debugging RTL designs using industry-standard EDA tools. Passionate about semiconductor technology, with a keen interest in front-end design, verification, and SoC development. Eager to contribute to innovative ASIC/FPGA design projects and grow as a verification engineer in a dynamic semiconductor environment.
Experience
Rtl Design Engineer
Jul 2025 — Present · Bengaluru, IN
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