Harikrishnan V
SoC Design Engineer at Arm
- Role
- Soc Design Engineer at Arm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Harikrishnan V
RTL Design Engineer with experience in RTL Design using VHDL/Verilog, Top Integration, Synthesis, Implementation, Functional and Timing Simulations, Design debugging using ILA, Static Timing Analysis, CDC, AXI, Low Power Design, 100G MAC, 5G NR Low PHY and oRAN Front haul interface.
Experience
Soc Design Engineer
Dec 2024 — Present
Education
TKM College of Engineering , Kollam
BTech - Bachelor of Technology, Electronics and Communications Engineering
2016 — 2020
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