Harika Gorla
Senior Physical Design Engineer @7Rays Semiconductors
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WORK HISTORY
Senior Physical Design Engineer @7Rays Semiconductors
IN
EDUCATION
Gudlavalleru Engineering College, Seshadri Rao Knowledge Village, Gudlavalleru, PIN-521356(CC-48)
Electrical and Electronics Engineering
ABOUT HARIKA GORLA
I have 3 years of experience as a Physical Design Engineer at Cerium Systems, specializing in the full RTL-to-GDSII flow. Proficient in key physical design tasks such as floorplanning, placement, clock tree synthesis (CTS), and routing. Adept in static timing analysis (STA), timing closure, and optimizing power, performance, and area (PPA) using advanced EDA tools (Synopsys ICC2, PrimeTime, FC and ICV).FEV, VCLP, Physical verification, Timing Caliber, crosstalk delay.Signal EM, IR/RV, Hot_nets, Hot_spots.various aspects of LVS (Layout vs. Schematic), DRC (Design Rule Check), ERC (Electrical Rule Check), Antenna, Density, Crosstalk, and other signoff checks.Extensive experience working on advanced technology nodes (e.g, 28nm, 10nm, 7nm, 3nm), with a solid understanding of foundry processes and design for manufacturing (DFM) practices.
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