Harika B
Design Verification Engineer | SystemVerilog | UVM | PCIe Gen4 | Functional & Protocol Verification | MS in ECE (IIT Chicago)
- Role
- Design Verification Engineer at Aspire Systems
- Location
- Chicago, IL, US
- LinkedIn followers
- 500 followers
About Harika B
I am a Design Verification Engineer with 3+ years of experience in verifying complex hardware systems using SystemVerilog, UVM, and industry-standard simulation tools. My expertise lies in building scalable testbenches, achieving coverage closure, and debugging critical issues to ensure protocol compliance and functional accuracy.I’ve worked on PCIe Gen4 IP, thin-film deposition control logic, and thermal/pressure control systems, delivering high-quality sign-off ahead of deadlines. Skilled in automation (Python, Jenkins) and compliance (ISO 13485, Polarion), I bring strong cross-functional collaboration skills and a passion for building efficient verification environments.Currently pursuing my M.S. in Electrical and Computer Engineering at IIT Chicago, I aim to contribute to cutting-edge SoC/ASIC verification and semiconductor design projects in the U.S. market.
Experience
Design Verification Engineer
Oct 2024 — Present · IL, US
Worked on verification of PCIe Gen4 IP core, collaborating with SoC architects and RTL designers during requirement gathering anddesign reviews, ensuring 100% alignment on functional and protocol specifications before verification kickoff.• Developed a comprehensive verification plan covering functional, corner-case, and performance scenarios using SystemVerilog andUVM, targeting 98% functional coverage and 100% assertion coverage for protocol compliance.• Created and maintained UVM testbench with directed and constrained-random stimulus, achieving over 96% functional coverage anduncovering critical protocol bugs during early verification phases, reducing downstream design rework by 30%.• Conducted protocol compliance checks and error injection testing using Synopsys VCS and QuestaSim simulators. Collaborated dailywith RTL engineers to debug and resolve 100% of high-priority bugs within verification cycles.• Delivered comprehensive verification reports, coverage closure documents, and bug analysis. Coordinated cross-team reviews andsuccessfully achieved 100% coverage closure and full compliance sign-off ahead of project deadline.
Education
R.V.R. & J.C. College of Engineering
Bachelor of Technology - BTech
Illinois Institute of Technology
Master's degree
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.