Hari Hemanth
Digital IC Design and Verification Engineer|| Strong interest in ASIC RTL-to-GDS flow (Cadence) || STUDENT OF ADITYA UNIVERSITY || Final Year || RTL Design and Verification Intern at KT semicon|| Content creator
- Role
- Rtl Design and Verification Intern at Kt Semicon
- Location
- Vizianagaram, AP, IN
- LinkedIn followers
- 500 followers
About Hari Hemanth
I am highly passionate about building a career as a Design Verification Engineer, where I can ensure the correctness, reliability, and efficiency of complex digital designs. My expertise is primarily in functional verification using Cadence tools, with a strong command of SystemVerilog-based testbench development and simulation using Cadence Xcelium.I have experience in writing constrained-random testcases, assertions, functional coverage models, and self-checking environments, enabling thorough validation of RTL designs. My project background includes verifying DSP modules such as approximate MAC-based DSP cores, linear convolution engines, and ALUs, where I applied both directed and random verification techniques to achieve coverage closure and detect corner-case bugs.Along with verification, I also have practical exposure to the RTL-to-GDSII flow using Cadence:Genus for logic synthesis and design optimizationInnovus for floorplanning, placement, routing, and PPA (Power, Performance, Area) analysisVirtuoso for custom/analog design explorationThis broader knowledge allows me to appreciate the interaction between front-end verification and back-end implementation, making my verification more effective and realistic.In addition, I regularly use Python and Shell scripting to automate regression runs, build reusable verification flows, and enhance productivity. I also practice waveform analysis and debugging using SimVision/Verdi (via Cadence flow) to identify issues quickly and accurately.My current focus is to master UVM methodology, expand my knowledge in low-power verification and formal property checking, and grow into a specialized Design Verification Engineer who can contribute to first-silicon success. I am driven by curiosity, teamwork, and continuous learning, and I enjoy collaborating with RTL designers and physical design engineers to deliver robust silicon solutions.
Experience
Rtl Design and Verification Intern
Jan 2026 — Present · Hyderabad, IN
Education
Zilla Parishad High School
SSC 10TH
Aditya University
Bachelor of Technology - BTech, Electronics and communication engineering
State Board of Technical Education and Training (SBTET), Andhra Pradesh
Diploma of Education, Electronics and Communications Engineering
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